As a general variable delay apparatus, there is a variable delay apparatus in which a plurality of delay elements are connected in series and the outputs of the delay elements are selected (for example, see Patent Reference 1). In order to reduce the apparatus scale, furthermore, a variable delay apparatus is configured by combining delay elements having a delay amount of N-th power of 2×t (t is the shortest delay time, and N is an integer) (for example, see Patent Reference 2).
FIG. 10 shows the configuration of the general variable delay apparatus disclosed in Patent Reference 1. Delay elements 1002a to 1002n are connected in series, an input signal 1001 and the outputs of the delay elements 1002a to 1002n are connected to a selector 1004, and an output signal 1005 is selected by a selection signal 1003, thereby configuring a variable delay apparatus in which the delay amount of the input signal 1001 is variable.
FIG. 11 shows the configuration of the general variable delay apparatus disclosed in Patent Reference 2. An N number of delay stages respectively configured by delay elements 1103, 1105, 1106 having a delay amount of (N−n)-th power of 2×t (t is the shortest delay time, and n is an integer from 1 to N), and multiplexers 1104, 1106, 1108 are connected in series, and internal signal paths in the delay stages are selected by an N-bit delay selection signal 1102, thereby configuring a variable delay apparatus in which the delay amount of the input signal 1101 is variable.
Patent Reference 1: JP-A-8-56143
Patent Reference 2: JP-A-6-196958